1. Field of the Invention
The present invention relates generally to a digital phase lock loop, and ore particularly, to a digital phase lock loop that generating output clock having wider frequency ranges than conventional approaches and no delay lookup circuit is required.
2. Description of the Prior Art
Phase lock loops (PLL) have been widely used in communication systems or the like, some frequently appeared applications such as extracting information from carried waves or synchronous signals usually employ PLLs to achieve their requirements. Typically, PLLs can be classified into analog- or digital-type PLL circuits. FIG. 1 represents a schematic diagram of a conventional analog PLL, which basically consists of a phase detector 102, a loop filter 104, and a voltage controlled oscillator (VCO) 106. Input signal Sia and the signal Soa output by the VCO 106 are together routed to the phase detector 102 for comparing their phases. An output voltage VPD according to the aforementioned comparison result is processed by the loop filter 104 to eliminate high frequency noises. A voltage VLF then outputs to VCO 106 for adjusting the currently oscillating frequency such that the phase deviation between Sia and Soa can be minimized. Typically, a low pass filter is usually used to construct the loop filter 104 because the high frequency signals will be removed in PLLs. However, analog circuits are very expensive because the loop filter 104 and VCO 106 are usually composed of resistance and capacitors conventionally, which also indicates that large spaces are occupied and required simultaneously. Nowadays, the advent of digital circuit technology brings the PLLs to be established by digital circuits such as flip-flops or logical gates (e.g., AND, OR, NOR, exclusive OR gates, and so on).
Please refer to FIG. 2, which shows a functional diagram representative of a conventionally digital PLL that includes an all-digital phase detector 202, an all-digital loop filter 204, a divider (DIV) 206, a digitally controlled oscillator (DCO) 208, and a fixed high frequency oscillator 210. In operations, the input reference clock Sid will be compared with the output clock of DIV 206 in all-digital phase detector 202 to obtain their phase differences. The comparison result is then processed by all-digital loop filter 204 to generate a control signal suitable for DCO 208. The DCO 208, which requires a reference clock generated by a fixed high frequency oscillator 210, outputs a locked signal Sod routed to DIV 206 for further processing instead of routed to all-digital phase detector 202 directly. DIV 206 that typically a programmable divider then divides the frequency of the reference clock provided from the fixed high frequency oscillator 210 before transferring to all-digital phase detector 202. The fixed high frequency oscillator 210 is practically a crystal oscillator having a high oscillating frequency, which is usually provided for generating a reference clock for the system it mounted therein. In the present days, DCO 208 described above is broadly employed in digital PLLs to replace the use of VCO 106 in analog PLLs, many schematics for DCO 208 are thus disclosed today. Descriptions of some structures associated with the invention are given hereinafter.
Please refer to FIG. 3A, which depicts a schematic diagram composed of fractional structure to generate the desired clock by dividing reference clock having high frequency conventionally. A waveform diagram generated by the structure of FIG. 3A is depicted in FIG. 3B. A clock CK_OSC generated by a fixed high frequency oscillator 302 is used as the base for generating an output clock SOF by the cooperation of a divider (DIV) 304, a fractional part set 306, and a selector 308. In operations, the relation between the frequency FCKxe2x80x94OSC of CK_OSC and the frequency FCKxe2x80x94DCO of the target clock can be described as:             F      CK_DCO        xc3x97    N    ⁢          xe2x80x83        ⁢          A      M        =      F    CK_OSC  
where A and M are internally controlled parameters of the fractional structure. For example, when FCKxe2x80x94OSC and FCKxe2x80x94DCO are respectively 32 and 13 MHz, the above equation will be:             F      CK_DCO        xc3x97    N    ⁢          xe2x80x83        ⁢          A      M        =            F      CK_OSC        =          32      =              13        xc3x97        2        ⁢                  xe2x80x83                ⁢                  6          13                    
Thus, A, M and N are 6, 13, and 2, respectively. In operations, the fractional part set 306 generates a comparison result SD to decide the frequency next output through SOF by using parameters A and M when triggered by SOF. For example, when M and FCKxe2x80x94OSC are respectively 13 and 32 MHz, a clock having an average frequency of 13 MHz can be derived by using clocks of 16 and 10.67 MHz because 13 falls in a range of 16 MHz(32/2) to 10.67 MHz(32/3). At the beginning, a clock having a frequency equal to a half of FCKxe2x80x94OSC (i.e., 16=32/N, N=2) can be output as SOF because A (6) is smaller than M (13). At the second period, the clock having a frequency equal to a half of FCKxe2x80x94OSC is still output as SOF because A plus itself (i.e., A=6) to obtain 12 which is also smaller than M (13). Next at the third period, due to the added value becomes 18 (12+6) is larger than M, the fractional part set 306 outputs an overflow signal to force the selector 308 to output a clock having a frequency of 10.67 (32/(2+1)) MHz as SOF. Additionally, control signals from the loop filter 204 can adjust the frequency of SOF, for example, a carry signal or a borrow signal can slow down or speed up the output clock SOF, respectively.
A very simple structure is obviously offered by FIG. 3A to generate a clock having an average frequency equal to the target clock. Accordingly, the manufacture cost can be significantly degraded based on fractional structure, and furthermore the duty cycle of the generated clock is 100%. However, the output jitter generated by the fractional structure usually too large to make the systems abnormally perform. Please refer to FIG. 3B again, the output jitter will be larger when the frequencies of the target clock and FCKxe2x80x94OSC are getting closer because the frequency of SOF switches at (FCKxe2x80x94OSCxc3x971/N) and (FCKxe2x80x94OSCxc3x971/(N+1)). For example, SOF will varies from 10.67 to 16 MHz when N=2. However, SOF will varies from 16 to 32 MHz when N=1, and the output jitter will be:
1/Nxe2x88x921(N+1)=1/1xe2x88x921/2=1/2UI(Unit Interval)
which is usually out of the current jitter specification (e.g., 1/8 or 1/6 UI). On the other hand, the period of the clock generated by the fractional structure is unstable although its average frequency coincide the jitter specification of the target clock such as period indicated by a label 310 in FIG. 3B. The system applied the fractional structure may occasionally abnormally work because the unstable period may result in some elements of the system work abnormally. Accordingly, the fractional structure are typically employed in those applications that the frequency difference between reference clock and target clock is larger enough, for example, 100 and 32 MHz, respectively. It is especially unsuitable to use the fractional structure for the other applications that quick clocks are desired.
The second DCO structure is so-called phase-hopping DCO structure, FIGS. 4A and 4B respectively illustrates the schematic and timing diagram according to the conventional phase-hopping structure. The phase-hopping structure shown in FIG. 4A basically encompasses a fixed high frequency oscillator 402, a divide-by-N divider (DIV) 404, an L-tapped delay line 406, a multiplexer (MUX) 408, an adder 410, a log2(L)-bits latch 412, and an L-to-1 MUX. In operations, DIV 404 generates the target clock whose frequency equals to the quotient of FCKxe2x80x94OSC dividing by an integer. For example, an oscillator 402 of 32 MHz clock can be divided by an integer 16 to obtain a target clock of 2 MHz. Output of the DIV 404 is routed into the log2(L)-bits latch 412 to generate an L-bit outputs as control signals input to L-to-1 MUX 414 for selecting output clock SOP from the cascade delay elements.
Control signals from external PLL such as from the loop filter 204 can be input into a carry or borrow terminal of the muiltiplexer for adjusting the frequency of output clock SOP. For example, a borrow signal will cause MUX 408 to select xe2x80x9cxe2x88x921xe2x80x9d to decrease one in log2(L)-bits latch 412, thus slow down the output clock from the L-to-1 MUX 414 as described by label 416 in FIG. 4B. In contrast, a carry signal will force MUX 408 to select xe2x80x9c1xe2x80x9d to fasten the output clock SOP. If PLL works stable, MUX 408 will outputs xe2x80x9c0xe2x80x9d to force log2(L)-bits latch 412 to freeze at current frequency. Some advantages offered by the phase-hopping structure. Firstly, a very simpler structure is provided by the phase-hopping structure, for example, by applying logic gates can easily construct the phase-hopping structure. Secondly, the output jitter of the phase-hopping structure also achieves the designed requirement (e.g., 16 UI), and the average frequency of the output clock is substantially the same as the target clock. However, a fatal disadvantage is that the frequency of CK_OSC must be integer times for all derived target clocks, which indicates that only some applications can employ the phase-hopping scheme.
Please refer to FIGS. 5A and 5B, which respectively illustrate a schematic diagram and a waveform diagram of a conventional tapped delayed-line DCO structure. Typically, tapped delay-line DCO structure generates a starting clock that faster than the required target clock by using a programmable divider (DIV) 508 to divide CK_OSC from oscillator 510, the starting clock is then routed to an L-bits latch 504. L-bits latch 504 then outputs signals to an L-to-1 MUX 502 that is further controlled by a delay look-up circuit 512 to control the output clock SOT. Please note that a programmable divider (DIV) 514 and a selector 516 having the same functions as in FIG. 3A can be used to generate the target clock, for example, the parameters A, M, N are input to the selector 516 in advance. Output signal of the selector 516 is then routed to delay look-up circuit 512 to control SOT output from L-to-1 MUX 502. Moreover, the delay interval of each delay element of the L-taps delay line 504 will vary as processes which the delay elements are fabricated. And furthermore, additional parameters, such as the environment temperature that the delay elements are allocated, will bring the designed delay interval to be somewhat distorted. However, tapped delayed-line DCO structure employs a cycle detector 506 to obtain phase differences between the currently delay interval of the delay element and the output clock SOT, and then directs the detection results to delay look-up circuit 512. Therefore, SOT will be a clock that satisfies the requirements of applications even the delay interval is varied with environment.
Although the tapped delayed-line DCO structure offers some important advantages, such as a relative small output jitter, the frequency of the generated clock equals to the counterpart of the target clock as described in FIG. 5B, and duty cycle is 1:1; however, a complicated and tremendous delay look-up circuit is required to store a great deal of information. Furthermore, incredibly additional information is needed even only one delay element is increased in the tapped delayed-line, which indicates that the design of the delay look-up circuit becomes a manufacture and time costly job.
Obviously, the conventional approaches can overcome/bring some disadvantages/advantages simultaneously, however, the provided functions and manufacture costs become a trade-off that can not satisfy requirements of the modern technologies. A need has been arisen to disclose a circuit and accompanied with a method that can overcome the disadvantages of the conventional DCO structures and preserve the advantages of less manufacture cost and precisely controlling frequencies of the output clocks.
The principal object of the invention is to provide a digitally controlled oscillator that satisfies the designed jitter specification and accompanied with a simple structure.
The other object of the invention is to provide a digitally controlled oscillator that adjusts its output clocks with no delay look-up circuit.
According to the above objects, the present invention discloses a DCO circuit that combines the conventionally fractional and tapped delayed-line structures to generate the required target clocks, the build-in tapped delayed-line can also precisely control the output clocks as conventionally. Frequencies and phases between the required target clock generated by a fractional structure and the output clock generated by a tapped delay-line are compared to drive a K-counter loop filter for counting. When the output clock is faster than the target clock to force the stored value of the K-counter loop filter increasing to a first preset threshold, a control logic will be driven to slow down the output clock by controlling outputs of the tapped delay-line. On the other hand, the control logic will also be driven to speed up the output clock by controlling outputs of the tapped delay-line when the output clock is slower than the target clock and forces the stored value of the K-counter loop filter to decrease to a second preset threshold. The aforementioned adjusting steps keep going until the output clock is substantially the same with the target clock.
Additionally, signals from external of the disclosed DCO circuit are routed into the fractional structure to change the frequency of the target clock, which indicates that the output clock can be properly calibrated according to environment parameters without additional elements or circuits.